1. Field of the Invention
The present invention relates to a pipeline analog-to-digital converter (ADC), and more particularly, to a pipeline ADC that can minimize a sampling error without a front-end sample-and-hold amplifier (SHA).
2. Discussion of Related Art
Video systems such as high-definition televisions (HDTVs) require a high-performance ADC having a high resolution of 12 bits to 14 bits and a high sampling rate of tens of MHz.
Various known ADCs employ a pipeline structure to meet the requirements of high-speed signal processing and high resolution.
FIG. 1 is a block diagram of a conventional pipeline ADC 100, and FIG. 2 is a block diagram of a first sub-ranging ADC ADC1 shown in FIG. 1.
Referring to FIG. 1, the conventional pipeline ADC 100 includes a front-end SHA 110 that samples and holds an analog input signal Vin, first to K-th (where K is an integer equal to or larger than 2) sub-ranging ADCs ADC1, ADC2, . . . , ADCK that digitize parts of the analog input signal Vin in sequence, a digital correction circuit 140 that corrects digital codes output from the respective sub-ranging ADCs ADC1, ADC2, . . . , ADCK and outputs a final N-bit digital code, and a clock signal generator 150 that provides first and second clock signals Q1 and Q2 to the respective sub-ranging ADCs ADC1, ADC2, . . . , ADCK.
Referring to FIG. 2, the first sub-ranging ADC ADC1 includes a flash ADC 120 that digitizes a part of the analog input signal Vin and outputs digital codes, and a multiplying digital-to-analog converter (MDAC) 130 that amplifies a residue voltage that remains after the part of the analog input signal Vin is digitized by the flash ADC 120 and outputs the amplified residue voltage. The flash ADC 120 includes a sample/hold (S/H) 121, a plurality of preamplifiers 123, and plurality of latches 125, and the MDAC 130 includes an S/H 131, an adder 133, a residue voltage amplifier 135, and a DAC 137. Here, the S/H 121, 131 are passive sampling RC-networks including a plurality of switched-capacitors, respectively.
In the pipeline ADC 100 having the above-mentioned structure, the front-end SHA 110 samples an input signal during a half cycle of an operation clock, holds the sampled input signal during the other half cycle, and simultaneously provides the sampled input signal to the flash ADC 120 and the MDAC 130 of the first sub-ranging ADC ADC1, thereby minimizing a sampling error that may occur between the two blocks.
However, the front-end SHA 110 is an active sampling circuit including one amplifier and a plurality of switched-capacitors, and thus consumes more power with increase in the operating speed and resolution of the pipeline ADC 100. Also, the area of the ADC 100 increases due to the multiple capacitors included in the SHA 110. Furthermore, since the front-end SHA 110 is disposed at the front end of the pipeline ADC 100, noise and the non-linear characteristic of the multiple capacitors and amplifier included in the front-end SHA 110 may deteriorate performance of the entire pipeline ADC 100.
To reduce the power consumption and area, the front-end SHA 110 may be removed. In this case, however, points in time where the flash ADC 120 and the MDAC 130 of the first sub-ranging ADC ADC1 sample the analog input signal Vin become different from each other. Thus, it cannot be ensured that the flash ADC 120 and the MDAC 130 sample the same value, that is, a serious sampling error may occur between the flash ADC 120 and the MDAC 130.